In a DRAM, in order to read the data (i.e., the charge stored in the capacitor) which is stored in a cell, the cell is selected by designating a word line and a bit line which are arranged in the longitudinally and laterally. Thus the information of the cell is read by being transmitted to a sense amplifier, and the information thus read out is transmitted through a data bus to the outside of the DRAM.
Recently, large scale DRAM chips have been developed, and the number of cells connected to one bit line has been increased. Further, the unit area of the cell has been reduced, and the gaps between word lines and bit lines have been narrowed, with the result that the power consumption has been increased, and that the sensing noise has also been increased, thereby aggravating the reliability of DRAM cell.
In order to describe the conventional technique for the bit line structure, a simple circuit is illustrated in FIG. 1.
Cell arrays AR0, AR1, AR2, . . . respectively include a plurality word lines WL1, WL2, . . . WLi . . . and bit lines BL and /BL. The bit lines are made of a conductive material such as polysilicon or a metal. Each of the bit lines is connected to a bit line selecting switch 12. The bit line selecting switch 12 is disposed between the cell arrays AR0 and AR1, and is connected to the sense amplifier.
A pair of the bit line selecting switch 12 to which the bit lines BL and /BL are connected are connected to a sense amplifier, and two pairs of the bit lines BL and are /BL respectively connected to the upper side and the lower side of the sense amplifier. That is, four of the bit line switches are connected in such a manner that four bit lines are connected to each of the sense amplifiers.
In the illustrated structure, the sense amplifier is a shared sense amplifier which is shared by two pairs of the bit lines which are included in the cell arrays AR0 and AR1.
A pair of the bit lines (bit line and /bit line, hereinafter "/" means "Bar") connected to the sense amplifier belongs to one cell array, and the other pair of the bit line (bit line and/bit line) belongs to another cell array.
The operation of the conventional technique as illustrated in FIG. 1 will be described as to its operations.
In order to select a cell CLi which belong to the cell array AR0, if a word line WLi is selected, then the information which is stored in the cell CLi is loaded on the bit line.
Under this condition, all the data of the cells which are connected to the same word line are loaded on the respective bit lines.
The sense amplifier SAi reads the data by comparing and amplifying the voltages of the bit lines BL and /BL through the bit line selecting switches.
Thus a bit line BLi is selected, and the information of the cell CLi is read out.
In this way, if the information which is stored in the cell is loaded on a bit line of the sense amplifier, the information is amplified to be stored into the capacitor again. Then the word line is deactivated, and the sense amplifier and the bit lines are restored to the original status.
In the above described conventional technique, when the layout is made within the limited area, the number of memory cells connected to a bit line is very large, while the capacitance of the bit line is enlarged. Therefore, when the chip is operated, the current flowing through the bit line is increased. Further, the increase of the capacitance between bit lines may cause errors during the reading.